Sarcina Technology to custom package cryo chips for extremely low temperatures
(Image credit: sureCore).Sarcina, a semiconductor packaging expert, has designed a solution specifically for use at cryogenic temperatures. The packaging is custom-designed for sureCore’s new range of cryogenic IP after successfully testing chips with 180 nm and 22 nm process nodes.
Paul Wells, sureCore’s CEO, says: “Reliable, robust, cryo-ready chip packaging is a necessity in harsh, low-temperature environments, and to ensure this, we partnered with Sarcina, whose specialist package design expertise is second to none.”
Larry Zu, Sarcina’s CEO, adds: “We have developed a reputation as the ‘go-to’ design expert for companies needing to push the boundaries of current packaging technology.”
“Whether this be for complex multi-chip 3D solutions, or, as in this case, for extreme low temperature operation, our experience and know-how allowed us to develop a custom BGA package specially for cryogenic temperatures,” he continues.
Near absolute zero temperature packaging
The consortium by sureCore, funded by the UK’s national agency Innovate UK, is an ecosystem of companies that offers the expertise and core competencies needed to develop cryo-tolerant semiconductor IP for the quantum computing space.
The company’s Static Random Access Memory, an essential building block for digital sub-systems, is able to cooperate at temperatures ranging from from 77 K (-196 degrees Celsius) down to the near absolute zero temperatures needed by quantum computers.
Sarcina Technology provides a custom solution to this requirement, specializing in advanced semiconductor package design for high-performance computing AI chips and high-performance communication silicon photonics chips.
The company, founded in 2011, also offers a comprehensive, one-stop solution for semiconductor packaging, testing, qualification and production.
Sarcina Technology already has a proven track record of 100% “right-the-first-time” advanced packaging and delivers wafer-to-production services that minimize overhead and accelerate time-to-volume.
In an interview with Packaging Insights, Zu told us about the company’s latest innovations and how it is addressing advanced packaging costs with its wafer-in and product-out technology, which can decrease the high costs of maintaining a hardware team for packaging, testing and production.
